Power Electronics & Energy Advanced 24 min

High-Efficiency Synchronous Buck DC-DC Converter Design

Design, calculate, build, and test a 24V-to-5V 5A synchronous buck converter with 96% efficiency, low ESR output filtering, and closed-loop feedback.

2. Prerequisites & Background Theory:

Inductor volt-second balance, capacitor charge conservation, MOSFET gate charge Qg, and Bode loop stability.

STEP 1

Goal & Engineering Objectives

Construct a switch-mode DC-DC converter stepping down 24V unregulated DC to 5.0V regulated DC at up to 5A continuous current with less than 25mV peak-to-peak output voltage ripple.

STEP 2

Governing Mathematical Formulation & Physics

                  Volt-Second Balance:
$$(V_{in} - V_{out}) D T_s = V_{out} (1 - D) T_s \implies V_{out} = D \cdot V_{in}$$

Inductor Sizing for 30% Ripple Ratio (Delta I_L = 0.3 * I_out):
$$L = \frac{V_{out} (1 - D)}{\Delta I_L \cdot f_{sw}}$$

Output Capacitor ESR Ripple Contribution:
$$\Delta V_{ESR} = \Delta I_L \cdot R_{ESR}, \quad \Delta V_C = \frac{\Delta I_L}{8 f_{sw} C_{out}}$$
Synchronous rectification replaces the freewheeling diode drop (0.5V) with an active MOSFET channel (I^2 * RDS(on)), boosting efficiency by over 8%.                

STEP 3

System Architecture & Block Flow Diagram

[24V DC Source] --> [LC EMI Filter] --> [High-Side & Low-Side MOSFETs]
                                                    |
                                          [Switch Node (SW)]
                                                    |
                                      [Molded Inductor (10µH)]
                                                    |
[Type-II Compensation] <-- [Divider FB] <-- [Polymer Capacitors (2x 100µF)] --> [5V 5A Load]

STEP 4

Required Hardware Bill of Materials (BOM)

Hardware Component	Qty	Engineering Specification
TPS40170 Synchronous Buck Controller IC	1	Wide 4.5V to 60V input, 300kHz-600kHz programmable
Dual N-Channel Power MOSFETs (CSD18532Q5B)	2	60V, 100A, 2.5mΩ RDS(on)
Molded Shielded Power Inductor (XAL1010-103MEB)	1	10 µH, 11.5A Isat, 8.5mΩ DCR
Aluminum Polymer Capacitors	2	100 µF 16V, 12 mΩ ESR
High-Frequency Ceramic Capacitors (1210)	4	22 µF 50V X7R input bypass
Precision Resistors (0603 0.1%)	6	Feedback divider and loop compensation components

Look up component pinouts in Components Catalog →

STEP 5

Wiring, Pinout & Schematics Mapping

                  • Connect VIN supply pins to ceramic input bypass caps directly at high-side MOSFET drain.
• Connect high-side source and low-side drain to Switch Node (SW) pad.
• Connect SW pad through 10µH power inductor to 5V VOUT rail.
• Connect bootstrap capacitor (100nF) between BOOT and SW pins of the controller.
• Connect feedback resistor divider (10kΩ and 1.43kΩ) from VOUT to FB pin (0.69V reference).
• Star-ground: Bond power GND plane to analog control AGND plane at a single point under the IC.                

STEP 6

Firmware Implementation & Algorithms

// C++: Buck Converter Component Sizing & Efficiency Simulator
#include <iostream>
#include <cmath>

struct BuckCalculations {
    double vin, vout, iout, fsw;
    double d, l_min_uh, delta_il, p_conduction_w, efficiency_pct;
    
    void compute(double rds_on_ohm, double dcr_ohm) {
        d = vout / vin;
        delta_il = 0.30 * iout; // 30% ripple ratio
        l_min_uh = ((vin - vout) * d) / (fsw * delta_il) * 1e6;
        
        // Conduction losses
        double p_fet_high = d * (iout * iout) * rds_on_ohm;
        double p_fet_low  = (1.0 - d) * (iout * iout) * rds_on_ohm;
        double p_inductor = (iout * iout) * dcr_ohm;
        p_conduction_w = p_fet_high + p_fet_low + p_inductor;
        
        double p_out = vout * iout;
        efficiency_pct = (p_out / (p_out + p_conduction_w + 0.35)) * 100.0;
    }
};

int main() {
    BuckCalculations buck = { 24.0, 5.0, 5.0, 400000.0 };
    buck.compute(0.0035, 0.0085);
    std::cout << "Required Inductance: " << buck.l_min_uh << " uH\n";
    std::cout << "Inductor Current Ripple: " << buck.delta_il << " A\n";
    std::cout << "Calculated Efficiency: " << buck.efficiency_pct << " %\n";
    return 0;
}

Simulate and Edit in Coding Lab

STEP 7

Bench Testing & Waveform Verification

                  1. Power on with current-limited 24V supply: Verify 5.02V output with zero load.
2. Connect AC-coupled oscilloscope probe with ground spring across VOUT: Verify ripple is under 18 mVp-p.
3. Step load from 1A to 5A with electronic load: Verify transient voltage dip is less than 120 mV and recovers within 50 µs.                

STEP 8

Troubleshooting & Common Failure Modes

                  • Problem: High-side MOSFET overheats or fails immediately upon power-on.
  Solution: Shoot-through cross-conduction. Increase gate driver dead-time from 20ns to 45ns.
• Problem: Excessive ringing on SW switch node exceeding 35V.
  Solution: Parasitic loop inductance in input loop. Solder a 2.2Ω + 1nF RC snubber from SW to PGND.
• Problem: Output voltage oscillates at 15 kHz under heavy load.
  Solution: Loop instability. Increase compensation resistor to widen phase margin to > 55 degrees.                

STEP 9

Extensions & Undergraduate Research Challenges

                  1. Implement multi-phase interleaved buck topology to divide 10A current across two 180° out-of-phase stages.
2. Add digital telemetry via PMBus / I2C monitoring real-time input voltage, output current, and MOSFET junction temperatures.                