Embedded Systems & IoT Intermediate 22 min

High-Speed SPI NOR Flash Black-Box Flight Data Logger

Log 100Hz aerospace telemetry frames to an external Winbond W25Q128 16MB SPI Flash chip using DMA double-buffering and wear-leveling.

2. Prerequisites & Background Theory:

SPI bus modes (CPOL/CPHA), flash page programming vs sector erasing, and DMA double-buffering.

STEP 1

Goal & Engineering Objectives

Stream high-density flight telemetry frames at 100 Hz to non-volatile SPI flash memory without blocking the primary flight stabilization loop.

STEP 2

Governing Mathematical Formulation & Physics

                  NOR Flash Architecture Constraints:
• Read access: Byte-level random access up to 104 MHz clock.
• Page Programming: Maximum 256 bytes per write command. Bits can only be flipped from '1' to '0'.
• Sector Erasing: Smallest erasable block is a 4 KB Sector (flips all bits back to '1'). Erase operation takes ~45 ms.

Double-Buffering Throughput:
While DMA transfers Buffer A (256 bytes) over SPI to Flash Page Program, the CPU accumulates sensor readings in Buffer B.
$$t_{frame} = \frac{256\text{ bytes} \times 8\text{ bits}}{20\text{ MHz}} + t_{prog\_internal} \approx 102.4\,\mu s + 700\,\mu s = 802.4\,\mu s$$
Well within the 10 ms (100 Hz) frame interval.                

STEP 3

System Architecture & Block Flow Diagram

[IMU / Barometer / GPS] --(Sensors 100Hz)--> [Ring Buffer in RAM (2x 256B)]
                                                     |
                                         (DMA Stream Peripheral Transfer)
                                                     v
                                         [SPI Controller @ 20 MHz]
                                                     |
                                                     v
                                    [Winbond W25Q128 Flash (16 MB)]

STEP 4

Required Hardware Bill of Materials (BOM)

Hardware Component	Qty	Engineering Specification
Winbond W25Q128JV 128Mbit (16MB) SPI NOR Flash	1	133 MHz SPI, 2.7V - 3.6V, SOIC-8
STM32F4 or ESP32-S3 Microcontroller	1	Hardware SPI with DMA controller
100 nF Ceramic Bypass Capacitor	1	Place directly adjacent to Flash VCC pin
10 kΩ Resistor	2	Hold /WP (Write Protect) and /HOLD pins HIGH

Look up component pinouts in Components Catalog →

STEP 5

Wiring, Pinout & Schematics Mapping

                  • Flash Pin 1 (/CS) -> MCU GPIO PA4 (Software or Hardware Chip Select)
• Flash Pin 2 (DO / MISO) -> MCU SPI1_MISO (PA6)
• Flash Pin 3 (/WP) -> 3.3V Rail (Disables hardware write protect)
• Flash Pin 4 (GND) -> System Ground Plane
• Flash Pin 5 (DI / MOSI) -> MCU SPI1_MOSI (PA7)
• Flash Pin 6 (CLK) -> MCU SPI1_SCK (PA5)
• Flash Pin 7 (/HOLD) -> 3.3V Rail (Disables bus hold)
• Flash Pin 8 (VCC) -> 3.3V Clean Rail (with 100nF cap to GND)                

STEP 6

Firmware Implementation & Algorithms

// C: SPI Flash 256-Byte Page Program with Write-Enable (ANSI C)
#include <stdint.h>
#include <stdbool.h>

#define W25Q_WRITE_ENABLE       0x06
#define W25Q_PAGE_PROGRAM        0x02
#define W25Q_READ_STATUS_REG_1  0x05

extern void spi_select_cs(void);
extern void spi_deselect_cs(void);
extern void spi_transfer_bytes(const uint8_t *tx, uint8_t *rx, uint16_t len);

void w25q_wait_busy(void) {
    uint8_t cmd = W25Q_READ_STATUS_REG_1;
    uint8_t status = 0;
    do {
        spi_select_cs();
        spi_transfer_bytes(&cmd, NULL, 1);
        spi_transfer_bytes(NULL, &status, 1);
        spi_deselect_cs();
    } while (status & 0x01); // Poll BUSY bit 0
}

void w25q_write_page(uint32_t pageAddress, const uint8_t *data256) {
    w25q_wait_busy();
    
    // Send Write Enable Latch (WEL)
    uint8_t cmd_we = W25Q_WRITE_ENABLE;
    spi_select_cs();
    spi_transfer_bytes(&cmd_we, NULL, 1);
    spi_deselect_cs();

    // Send Page Program Command + 24-bit Address
    uint8_t header[4];
    header[0] = W25Q_PAGE_PROGRAM;
    header[1] = (uint8_t)(pageAddress >> 16);
    header[2] = (uint8_t)(pageAddress >> 8);
    header[3] = (uint8_t)(pageAddress);

    spi_select_cs();
    spi_transfer_bytes(header, NULL, 4);
    spi_transfer_bytes(data256, NULL, 256); // 256-byte payload
    spi_deselect_cs();
}

Simulate and Edit in Coding Lab

STEP 7

Bench Testing & Waveform Verification

                  1. Read JEDEC ID register (Command 0x9F): Verify response returns Manufacturer 0xEF and Memory Type 0x4018.
Erase Sector 0 and verify all bytes read 0xFF.
Write a 256-byte test sequence; read back and verify 100% bit parity match.
Log 60 seconds of telemetry at 100 Hz: Power down, dump flash over serial, and verify zero dropped log frames.                

STEP 8

Troubleshooting & Common Failure Modes

                  • Problem: Flash reads all 0xFF even after writing.
  Solution: Write Enable command (0x06) was not issued prior to Page Program, or target sector was not erased prior to writing.
• Problem: Data corrupts past byte offset 256.
  Solution: Page Address wrapping. If a write exceeds the 256-byte boundary, internal flash address wraps back to 0 of the current page, overwriting starting bytes.
• Problem: SPI clock waveform exhibits ringing on oscilloscope.
  Solution: Slew rate too high. Add 33Ω series damping resistors on SCK and MOSI lines close to the MCU.                

STEP 9

Extensions & Undergraduate Research Challenges

                  1. Integrate LittleFS (fault-tolerant embedded file system) on top of NOR flash for structured CSV telemetry files.
2. Enable Quad-SPI (QSPI) 4-bit bus mode to quadruple read throughput during post-flight USB log downloading.                