Microcontrollers Advanced Level 20 min

STM32 ARM Cortex-M: Hardware Timers & Direct Memory Access (DMA)

ARM Cortex-M NVIC interrupt nesting, advanced timer PWM generation, dead-time insertion, and zero-CPU-overhead DMA circular transfers.

Prerequisites: C pointers, binary bitwise manipulation, microcomputer bus architecture, and basic interrupt theory.

1. Overview & Concept Definition

An architectural analysis of high-performance 32-bit ARM Cortex-M microcontrollers (such as STM32F4/G4 series) focusing on hardware peripheral interconnects and direct autonomous memory transfers.

2. Engineering & Industrial Significance

Industrial motor control, digital power conversion, and high-speed audio/telemetry where CPU overhead must remain near zero while peripherals service megasample-per-second streams.

3. Physical Working Principle & Transducer Dynamics

Advanced Control Timers (TIM1/TIM8) contain 16/32-bit auto-reload counters with programmable prescalers, complementary outputs, and hardware dead-time generators. The Direct Memory Access (DMA) controller acts as an autonomous bus master, moving multi-word blocks between memory and peripherals without waking or stalling the Cortex-M processor core.

4. Governing Equations & Mathematical Models

Timer Output Frequency: $f_{PWM} = \frac{f_{TIMCLK}}{(PSC + 1) \times (ARR + 1)}$

Timer Duty Cycle: $D = \frac{CCR}{(ARR + 1)} \times 100\%$

Dead-Time Duration: $t_{dt} = DTG \times T_{dts}$

DMA Bus Bandwidth: $BW = f_{bus} \times \text{BusWidth}_{bytes} \times (1 - \text{ArbitrationOverhead})$

5. Practical Implementation

// C (STM32 LL / Register): Sizing 20kHz complementary PWM on 84MHz Timer
// PSC = 0, ARR = 4199 => f = 84,000,000 / (1 * 4200) = 20,000 Hz (20 kHz)
void configure_timer_pwm(void) {
    TIM1->PSC = 0;             // Prescaler: full 84 MHz clock
    TIM1->ARR = 4199;          // Auto-reload value: 20 kHz period
    TIM1->CCR1 = 2100;         // 50% duty cycle
    TIM1->BDTR |= (50 << 0);   // Set dead-time generator (~600ns protection)
    TIM1->CCER |= (1 << 0) | (1 << 2); // Enable CH1 and CH1N complementary outputs
    TIM1->CR1 |= (1 << 0);     // Enable counter
}

6. Common Engineering Pitfalls & Troubleshooting

Frequent Engineering Pitfalls

Missing cache coherency on Cortex-M7: When D-Cache is enabled, the CPU reads stale cached memory instead of fresh data written by the DMA controller. Mark DMA buffers as non-cacheable MPU regions or call SCB_InvalidateDCache_by_Addr().
Forgetting to enable peripheral clock in RCC: Reading or writing timer registers before calling RCC->APBxENR results in an immediate HardFault exception.

Diagnostic & Troubleshooting Checklist

Inspect HardFault Status Register (SCB->HFSR and CFSR) inside HardFault_Handler using a debugger to distinguish memory faults from bus errors.
Verify NVIC priority grouping: High-frequency motor control ISRs must have higher priority (lower numeric value) than serial communications to avoid jitter.

7. Applications & Physical Constraints

TYPICAL APPLICATIONS

Field-Oriented Control (FOC) 3-phase inverter modulation
High-frequency synchronous buck converter gate driving
Multi-channel real-time audio ADC/DAC streaming

PHYSICAL LIMITATIONS

Complex register configuration required compared to 8-bit microcontrollers.
DMA bus contention occurs when multiple high-bandwidth streams share the same AHB matrix.

Pinout & Interface Specs

PIN / SIGNAL	FUNCTION / ELECTRICAL SPEC
TIM1_CH1	High-side complementary PWM output pin
TIM1_CH1N	Low-side complementary PWM output pin (with hardware dead-time)
TIM1_BKIN	Hardware emergency brake input (instant PWM shutdown)
ADC1_IN	Analog input channel triggered by timer TRGO
SWDIO / SWCLK	Serial Wire Debug programming pins

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