ESP32 Dual-Core Architecture & FreeRTOS Task Pinning

1. Overview & Concept Definition

A powerful system-on-chip (SoC) featuring dual 32-bit Xtensa LX6 microprocessors running up to 240 MHz with integrated 2.4 GHz Wi-Fi, Bluetooth 4.2 BLE, and rich hardware peripherals.

2. Engineering & Industrial Significance

Enables running high-throughput network stacks (TCP/IP, MQTT, HTTP) alongside deterministic hard-real-time motor control loops without interference.

3. Physical Working Principle & Transducer Dynamics

The two cores (PRO_CPU Core 0 and APP_CPU Core 1) operate concurrently on shared 520 KB SRAM. The ESP-IDF framework runs a modified multi-core FreeRTOS scheduler. Core 0 typically handles network communications and background interrupts, while Core 1 executes time-critical control algorithms pinned via `xTaskCreatePinnedToCore()`. Inter-task communication uses thread-safe FreeRTOS Queues and binary semaphores.

// ESP-IDF / Arduino FreeRTOS: Pinning real-time control task to Core 1
TaskHandle_t ControlTaskHandle;

void controlLoopTask(void *parameter) {
    TickType_t xLastWakeTime = xTaskGetTickCount();
    const TickType_t xFrequency = pdMS_TO_TICKS(5); // Deterministic 200 Hz loop

    for (;;) {
        // Hard real-time sensor read and PID execution
        // ...
        vTaskDelayUntil(&xLastWakeTime, xFrequency);
    }
}

void setup() {
    xTaskCreatePinnedToCore(
        controlLoopTask,     // Task function
        "ControlTask",       // Name
        4096,                // Stack size in bytes
        NULL,                // Parameters
        configMAX_PRIORITIES - 1, // Highest application priority
        &ControlTaskHandle,  // Handle
        1                    // Pin to Core 1
    );
}

6. Common Engineering Pitfalls & Troubleshooting

7. Applications & Physical Constraints